This invention relates to a semiconductor integrated circuit device and also to a technique of manufacturing the same. More particularly, the invention relates to a technique effective for improving the property of adhesion between a bonding pad and an interlayer insulating film provided therebelow.
In order to prevent the separation of a bonding pad that will occur in the course of the step of sealing, with a tape carrier package (TCP), a semiconductor chip including an interlayer insulating film having a three-layered structure wherein a spin-on-glass (SOG) film is sandwiched between two silicon oxide films, Japanese Laid-open Patent Application No. Hei 10(1998)-247664 discloses a technique wherein a dummy wiring is provided below the bonding pad formed on the interlayer insulating film so as to increase an area of mutual contact of the two silicon oxide films at the lower region of the bonding pad, thereby suppressing the interfacial separation between the SOG film and the silicon oxide films.
In recent years, as a chip size is more reduced owing to a higher degree of integration of LSI, the bonding pad is also reduced in size.
We have found that there is being actualized a phenomenon wherein a stress exerted per unit area of a bonding pad increases at the time of wire bonding, and an uppermost Al (aluminum) wire constituting a bonding pad and a lower interlayer insulating film are separated from each other at the interface thereof. Especially, in the course of manufacture of MCP (multi chip package), there is used a KGD (known good die) technique in order to guarantee the quality of individual chips prior to assembling. In this case, a wire is bonded on the respective bonding pads upon inspection at the stage of individual chips and also at the package stage, under which we have found that the bonding pad is more liable to separate.
As a measure for preventing the separation of the bonding pad, it may occur that the bonding pad is constituted, for example, of a two-layered structure including an uppermost Al wire and a lower Al wire so as to increase strength thereof. In this case, however, the structure is so designed as to include an interlayer insulating film, which is made of silicon oxide whose hardness is higher than Al, interposed between the two Al wires. This will permit the hard layer insulating layer to be cracked when wire bonded, thereby causing the separation of the bonding pad.
An object of the invention is to provide a technique of suppressing the separation of a bonding pad.
The above and other objects, and novel features of the invention will become apparent from the description of the specification and accompanying drawings.
Typical embodiments of the invention are summarized below.
(1) The semiconductor integrated circuit device according to the invention comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, a first interlayer insulating film provided beneath a bonding pad formed on an upper wiring layer, and a first plug formed in the first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in the first interlayer insulating film wherein any wire connected to the first plug is not formed in a wiring layer beneath the first plug.
(2) The semiconductor integrated circuit device of the invention comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, a bonding pad formed on an upper wiring layer and connected to a wire, a first interlayer insulating film provided at a lower region of the wire, and a first plug formed in the first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in the first interlayer insulating film wherein any wire is not formed in a wiring layer below the first plug.
(3) The semiconductor integrated circuit device of the invention comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, a bonding pad formed at an uppermost wiring layer, a first interlayer insulating film provided beneath the bonding pad, a first plug formed in the first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in the first interlayer insulating film, and a wire formed in a wiring layer beneath the first plug and made of a third conductive film whose hardness is higher than that of a second conductive film constituting the uppermost wire.
(4) The method for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of:
(a) forming a wire in an element-forming region on a semiconductor substrate and further forming a first interlayer insulating film over the wire;
(b) etching the first interlayer insulating film in the element-forming region to form a first through-hole reaching the wire, and etching the first interlayer insulating film in a bonding pad-forming region to form a hole;
(c) forming a barrier metal film on the first interlayer insulating film comprising the inner surfaces of the hole and the inner surfaces of the first through-hole and forming a first conductive film containing as its main component a refractory metal on the upper portion of the barrier metal film so that the first conductive film is buried in the hole and the first through-hole;
(d) removing the first conductive film from the upper portion of the first interlayer insulating film by etching to form a first plug constituted of the barrier metal film and the first conductive film in the hole and also a second plug constituted of the barrier metal film and the first conductive film in the first through-hole;
(e) forming a second conductive film over the upper portion of said first interlayer insulating film; and
(f) etching the second conductive film so that an uppermost wire is formed on the first interlayer insulating film in the element-forming region and forming a bonding pad on the first interlayer insulating film in the bonding pad-forming region.